The present invention relates to a method and/or architecture for biasing cross-coupled switches or drivers generally and, more particularly, to a method and/or architecture for implementing a switched well technique for biasing cross-coupled switches or drivers.
A number of circuits such as charge pumps and some digital logic circuits use cross-coupled switches or drivers as bootstrapped output circuits. Conventional methods for biasing cross-coupled switches or drivers can result in leakage current and/or latch-up problems.
Referring to FIG. 1a, a schematic diagram of a conventional PMOS transistor cross-coupled switch/driver circuit 10 is shown. The circuit 10 has an input 12 and an input 14 that receive complementary clock signals xcfx86a and xcfx86b, respectively, and an output 16 that presents a signal OUTPUT. The clock signals xcfx86a and xcfx86b are non-overlapping. A load 32 is connected at the output 16.
The circuit 10 has a PMOS transistor 20, a PMOS transistor 22, a capacitance 24, a capacitance 26, a node 28, and a node 30. The transistors 20 and 22 are connected as cross-coupled switches. The N-wells of the transistors 20 and 22 are connected to the output 16.
The cross-coupled switches 20 and 22 are switched on and off every cycle of the clock signals xcfx86a and xcfx86b. Since the clock signals xcfx86a and xcfx86b are non-overlapping, the switches 20 and 22 can not turn on at the same time. When the signal xcfx86b is low, the transistor 20 is generally switched on. When the transistor is on, the charge stored at the node 28 is pumped to the load 32. Similarly, when the signal xcfx86a is low the transistor 22 is generally switched on. When the transistor 22 is on, the charge stored at the node 30 is pumped to the load 32. When the amplitude of the signals xcfx86a and xcfx86b is n*Vcc (where n is generally  greater than 1), the amplitude of the signal OUTPUT is approximately n*Vcc.
Referring to FIG. 1b, a schematic diagram of another conventional cross-coupled switch/driver circuit 10xe2x80x2 is shown. The circuit 10xe2x80x2 is implemented similarly to the circuit 10 of FIG. 1a except the circuit 10xe2x80x2 is implemented with additional devices 34 and 36 that have a supply voltage Vcc input and are coupled to nodes 28 and 30, respectively. The devices 34 and 36 are switches controlled by the signals SW1 and SW2 that can pump up the nodes 28 and 30 to approximately 2*Vcc when the amplitude of signals xcfx86a and xcfx86b n*Vcc and n=1. The output voltage OUTPUT can be approximately 2*Vcc.
Referring to FIG. 1c, a diagram of a circuit 10xe2x80x3 illustrating an NMOS transistor implementation of the circuit 10 of FIG. 1a is shown. The transistors 20xe2x80x3 and 22xe2x80x3 are NMOS transistors configured with a P-well and a deep N-well as described below in connection with FIG. 2b. The P-wells of the transistors 20xe2x80x3 and 22xe2x80x3 are generally biased as low as possible. The P-wells of the transistors 20xe2x80x3 and 22xe2x80x3 are biased by the signal xe2x88x92OUTPUT. When the amplitude of the signals xcfx86a and xcfx86b is xe2x88x92Vcc, the amplitude of the signal xe2x88x92OUTPUT can be approximately xe2x88x92Vcc.
Referring to FIG. 1d, a diagram of a circuit 10xe2x80x3 illustrating an NMOS transistor implementation of the circuit 10xe2x80x2 of FIG. 1b is shown. The amplitude of the signal xe2x88x92OUTPUT can be approximately xe2x88x92Vcc*2.
Referring to FIG. 2a, a diagram 40 illustrating a cross-section of an NMOS transistor 42 and a neighboring PMOS transistor 44 is shown. The PMOS transistor 44 illustrates the PMOS transistor 20 or 22 of FIGS. 1a and 1b. Because of the structure of the PMOS transistor 44, a vertical (parasitic) PNP transistor 46 is formed by the source 48 (emitter), the N-well 50 (base) and the substrate 52 (collector). When the source to drain voltage of the transistor 44 exceeds the base-emitter voltage (VBE) of the vertical PNP transistor 46, the vertical PNP transistor 46 turns on. Similarly, a lateral (parasitic) NPN transistor 54 is formed between the neighboring transistors 42 and 44 by the N-well 50 and the substrate 52 of the transistor 44 and the drain 56 of the transistor 42. When positive feedback occurs between the vertical transistor 46 and the lateral NPN transistor 54, the lateral NPN transistor 54 turns on. The base-emitter voltage VBE can be approximately 0.5 V. When the vertical transistor 46 or the lateral transistor 54 is on, leakage current and/or latch-up can occur through the lateral transistor 54. Leakage current can prevent the signal OUTPUT from reaching the expected value n*Vcc. A conventional method to avoid leakage current and/or latch-up is to bias the N-well 46 such that Vsourcexe2x88x92VNwell less than VBE when Vsource greater than =Vdrain.
Referring to FIG. 2b, a diagram 60 illustrating a cross-section of the NMOS transistor 20xe2x80x3 or 22xe2x80x3 of the FIGS. 1c and id is shown. Because of the structure of the twin-welled NMOS transistor 60, a vertical (parasitic) NPN transistor 62 and a lateral (parasitic) PNP transistor 64 are formed. The vertical transistor 62 is formed by the source 66 (emitter), the P-well 68 (base) and the deep N-well 72. The lateral transistor 64 is formed by the source 66 (P-region), the deep N-well 72, and the P-substrate 70. For the transistors 20xe2x80x3 and 22xe2x80x3 to function properly, the signal BIAS must bias the deep N-well 72 at a voltage greater than the voltage at the P-well 68 and the P-substrate 70. The P-substrate 70 is connected to a ground potential Vss. When the source to drain voltage of the transistor 20xe2x80x3 exceeds the base-emitter voltage (VBE) of the vertical NPN transistor 62, the vertical NPN transistor 62 turns on. The base-emitter voltage VBE can be approximately 0.5 V. When the vertical transistor 62 is on, leakage current and/or latch-up can occur. When positive feedback occurs between the vertical transistor 62 and the lateral transistor 64, the lateral PNP transistor 64 can latch up. A conventional method to avoid leakage current and/or latch-up is to bias the P-well 68 such that Vsourcexe2x88x92Vpwell less than VBE when Vsource less than Vdrain.
Referring to FIG. 3a, a diagram 80 illustrating waveforms of the circuit 10 of FIG. 1a is shown. The voltage at the node 28 is illustrated by a waveform 82. The voltage at the node 30 is illustrated by a waveform 84. The signal OUTPUT is illustrated by a waveform 86. Since the N-wells of the transistors 20 and 23 are connected to the output 16, the waveform 86 also illustrates the N-well bias voltages of the transistors 20 and 22. The waveforms 82 and 84 have a peak voltage level 88. The waveform 86 has a minimum voltage level 90. The difference between the voltage level 88 and the voltage level 90 (i.e., xcex94Vcon) can be in the range of 0.3-1.2 V depending on manufacturing process variations and operating temperature.
When xcex94Vcon is greater than the base-emitter voltage VBE for the transistor 20 or the transistor 22, a forward biased junction diode between the source and the drain of the transistor 20 or the transistor 22 can turn on causing leakage current and/or latch-up. Voltage drooping at the nodes 28 and 30 can cause a large xcex94Vcon. A conventional approach to reduce voltage drooping at the nodes 28 and 30 is to implement large values for the capacitances 24 and 26. Large values for the capacitances 24 and 26 can reduce xcex94Vcon, but will not eliminate the leakage current. Large values for the capacitances 24 and 26 can also require significant die area.
Referring to FIG. 3b, a diagram 80xe2x80x2 illustrating waveforms of the circuits 10xe2x80x3xe2x80x2 and 10xe2x80x3 of FIG. 1c and 1d, respectively, is shown. The waveform 86xe2x80x2 illustrates the P-well bias voltages of the transistors 20xe2x80x3 and 22xe2x80x3. The waveforms 82xe2x80x2 and 84xe2x80x2 cross the waveform 86xe2x80x2 at low voltage levels. The waveforms 82xe2x80x2 and 84xe2x80x2 have a minimum voltage level 88xe2x80x2. The waveform 86xe2x80x2 has a peak voltage level 90xe2x80x2. The difference between the voltage level 88xe2x80x2 and the voltage level 90xe2x80x2 is xcex94Vcon.
Another conventional approach for providing the well-bias voltage to the transistors 20 and 22 is to duplicate the circuit 10 of FIG. 1a without the load 32. The output of the duplicate circuit 10 is used to bias the N-wells of the transistors 20 and 22. However, duplicating the circuit 10 has the disadvantage of doubling the required die area.
A method and/or architecture that reduces leakage current and/or latch-up and does not use significant die area would be desirable.
The present invention concerns an apparatus comprising a circuit that may be configured to generate an output in response to a first and a second input. The circuit may be automatically biased in response to the first and second inputs.
The objects, features and advantages of the present invention include providing a method and/or architecture for switched well biasing for cross-coupled or bootstrapped switches and/or drivers that may (i) require little extra die area, (ii) reduce transistor body effect, (iii) bias a PMOS transistor N-well to a higher voltage potential of two inputs, (iv) bias an NMOS transistor P-well to a lower voltage potential of two inputs, (v) prevent junction diode forward biasing, (vi) prevent leakage current, (vii) prevent latch-up, and/or (viii) be easily implemented.